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| HM62832UH Series 32768-word x 8-bit High Speed CMOS Static RAM Features * High speed: Fast access time 15/20 ns (max) * Low Power Standby: 15 W (typ) (L-version) Operation: 675/600 mW (typ) * Single 5 V supply * Completely static memory No clock or timing strobe required * Equal access and cycle times * Common data input and output: Three state output * Directly TTL compatible: All inputs and outputs Ordering Information Type No. HM62832UHP-15 HM62832UHP-20 HM62832UHLP-15 HM62832UHLP-20 HM62832UHJP-15 HM62832UHJP-20 HM62832UHLJP-15 HM62832UHLJP-20 Access Time 15 ns 20 ns 15 ns 20 ns 15 ns 20 n 15 ns 20 ns 300-mil 28-pin plastic SOJ (CP-28DN) Package 300-mil 28-pin plastic DIP (DP-28NA) HM62832UH Series Pin Arrangement A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CS I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 (Top view) Pin Description Pin name A0 - A14 I/O0 - I/O7 CS WE OE VCC VSS Function Address Input/output Chip select Write enable Output enable Power supply Ground 2 HM62832UH Series Block Diagram VCC V SS A8 A13 A14 A12 A7 A6 A5 A4 A3 X-Address Buffers Row Decoder Memory Array 512 x 512 I/O0 * * * I/O Buffer Column I/O Column Decoder I/O7 WE OE Column Address Buffer A10 A0 A1 A2 A9 A11 CS Function Table CS H L L L OE X L H L WE X H L L Mode Standby Read Write Write VCC Current I SB , I SB1 I CC I CC I CC I/O Pin High-Z Dout Din Din Read cycle 1, 2, 3 Write cycle 1 Write cycle 2 Ref. Cycle Note: X : H or L 3 HM62832UH Series Absolute Maximum Ratings Parameter Supply voltage *1 *1 Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +7.0 -0.5 to V CC + 0.5 1.0 0 to +70 -55 to +125 -10 to +85 *2 *2 Unit V V W C C C Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Notes: 1. With respect to V SS 2. VCC and VT min = -2.5 V for pulse width 10 ns Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 -0.5 *1 Typ 5.0 0 -- -- Max 5.5 0 VCC + 0.5 0.8 Unit V V V V 1. VIL min = -2.0 V for pulse width 10 ns 4 HM62832UH Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) Parameter Input leakage current Output leakage current Operating VCC current Symbol |ILI| |ILO | I CC1 (-15)*3 I CC2 (-15) I CC1 (-20) I CC2 (-20) Standby V CC current I SB (-15) I SB (-20) Standby V CC current (1) Min -- -- -- -- -- -- -- -- Typ*1 -- -- 135 100 120 90 40 30 0.02 Max 2.0 2.0 170 120 150 110 60 50 2.0 mA CS V CC - 0.2 V 0 V Vin 0.2 V or VCC - 0.2 V Vin Unit A A mA mA mA mA mA Test Conditions VCC = 5.5 V Vin = VSS to V CC CS = VIH VI/O = VSS to V CC min cycle*2 2x min cycle min cycle 2x min cycle CS = VIH, min cycle I SB1 (L-version) -- -- Output low voltage Output high voltage VOL VOH -- 2.4 0.003 -- -- 0.1 0.4 -- V V I OL = 8 mA I OH = -4.0 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = 25C and not guaranteed. 2. CS = VIL, Iout = 0 mA 3. Access time version Capacitance (Ta = 25C, f = 1.0 MHz)*1 Parameter Input capacitance Output capacitance Note: Symbol Cin Cout Min -- -- Typ -- -- Max 6 10 Unit pF pF Test Conditions Vin = 0 V VI/O = 0 V 1. This parameter is sampled and not 100% tested. 5 HM62832UH Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.) Test Conditions * * * * Input pulse levels: VSS to 3.0 V Input rise and fall time: 4 ns Input and Output timing reference levels: 1.5 V Output load: See figures +5 V +5 V 480 Dout 255 30 pF*1 Dout 255 480 5 pF*1 Output load (A) Note: 1. Including scope and jig Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ and tOW) Read Cycle HM62832UH-15 Parameter Read cycle time Address access time Chip select access time Chip selection to output in low-Z Output enable to output valid Output enable to output in low-Z Chip deselection to output in high-Z Chip disable to output in high-Z Output hold from address change Note: Symbol t RC t AA t ACS t CLZ t OE t OLZ t *1 *1 CHZ *1 *1 HM62832UH-20 Min 20 -- -- 3 -- 0 0 0 3 Max -- 20 20 -- 10 -- 10 10 -- Unit ns ns ns ns ns ns ns ns ns Min 15 -- -- 3 -- 0 0 0 3 Max -- 15 15 -- 8 -- 7 7 -- t OHZ t OH 1. Transition is measured 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6 HM62832UH Series Read Timing Waveform (1)*1 (WE = VIH) t RC Address t AA OE t OE t OLZ CS t ACS t CLZ Dout t OHZ t CHZ Valid Data t OH Note: 1. Transition is measured 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. Read Timing Waveform (2) *1 (WE = VIH, CS = VIL , OE = VIL ) t RC Address t AA t OH Dout Valid Data t OH Note: 1. Transition is measured 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 7 HM62832UH Series Read Timing Waveform (3) *1, *2 (WE = VIH, OE = VIL ) t RC CS t ACS t CLZ Dout Valid Data t CHZ Notes: 1. Transition is measured 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 2.Address valid prior to or coincident with CS transition low. Write Cycle HM62832UH-15 Parameter Write cycle time Chip selection to end of write Address valid to end of write Address setup time Write pulse width *2 *3 *1, 4 HM62832UH-20 Min 20 12 15 0 12 0 0 0 10 0 3 3 Max -- -- -- -- -- -- 10 10 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns Symbol t WC t CW t AW t AS t WP t WR t OHZ t WHZ t DW t DH *1, 6 *5 *1, 4 Min 15 10 13 0 10 0 0 0 8 0 3 3 Max -- -- -- -- -- -- 7 7 -- -- -- -- Write recovery time Output disable to output in high-Z Write to output in high-Z Data to write time overlap Data hold from write time *6 Output active from end of write t OW t OH Output hold from address change Notes: 1. Transition is measured 200 mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested. 2. A write occurs during the overlap (tWP) to a low CS and a low WE. 3. t WR is measured from the earlied or CS or WE going high to the end of write cycle. 4. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 5. Dout is the same phase of write data of this write cycle. 6. If CS is low during this priod, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 8 HM62832UH Series Write Timing Waveform (1) t WC Address OE *1 t CW CS t AW t AS WE t OHZ t WP t WR Dout t DW Din Valid Data Note: 1. If the CS low transition occurs simultaneously with the WE low transition or after the opposite phase to the outputs must not be applied. t DH 9 HM62832UH Series Write Timing Waveform (2) (OE low Fixed)*4 t WC Address t CW *1 CS t AW t AS WE t WHZ Dout t DW t DH t OW *2 *3 t WR t WP t OH Din Valid Data Notes: 1. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 2.Dout is the same phase of write data of this write cycle. 3.Dout is the read data of next address. 4.WE must be high during all address transition except when device is disable with CS. 10 HM62832UH Series Low VCC Data Retention Characteristics (Ta = 0 to +70C) This characteristics is guaranteed only for L-version. Parameter VCC for data retention Symbol VDR Min 2 Typ -- Max -- Unit V Test Conditions CS V CC - 0.2V, Vin V CC - 0.2 V or 0 V < Vin 0.2 V Data retention current I CCDR -- 0 5 2 -- -- 50*1 -- -- A ns ms Chip deselect to data retention time t CDR Operation recovery time Note: 1. VCC = 3.0 V tR Low V CC Data Retention Timing Waveform Data retention mode V CC 4.5 V t CDR 2.2 V V DR CS 0V CS VCC - 0.2 V tR 11 HM62832UH Series Package Dimensions HM62832UHP/UHLP Series (DP-28NA) 36.00 28 37.32 Max 15 7.37 Max Unit: mm 1 2.20 Max 1.3 14 5.08 Max 7.10 7.62 0.51 Min 2.54 Min 0.25 - 0.05 0 - 15 + 0.11 2.54 0.25 0.48 0.10 HM62832UHJP/UHLJP Series (CP-28DN) 18.17 18.54 Max 28 15 Unit: mm 0.74 3.50 0.26 1 14 7.62 0.13 8.64 0.13 1.30 Max 0.80 0.43 0.10 1.27 0.10 0.35 6.76 + 0.16 - 12 0.21 2.40 + 0.24 - +0.25 -0.17 |
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